A multi-probe correlated bulk defect characterization scheme for ultra-thin high-к dielectric

Various characterization techniques such as charge pumping (CP) and its variants (MFCP, VT²CP), 1/f noise, random telegraph noise (RTN), stress-induced leakage current (SILC) etc. are being used to identify the trap location within the dielectric. However, the most defective regions within the SiO₂/HfO₂ gate stacks identified by various methodologies are often not unique, leading to different optimization strategies for the gate stack. To resolve this issue, we develop a single theoretical framework to self-consistently interpret the MFCP, RTN, and SILC. Our analysis not only provides a consistent interpretation of different experimental observations of MFCP, SILC and RTN, but also identifies the capabilities and limitations of these techniques in terms of trap probing region. We show that the transition of the quasi Fermi level plays a vital role for the probing region with CP, SILC and consequently the classical interpretations of trap location from these experiments are not always correct for composite HK transistors. We demonstrate that none of these techniques can (in isolation) unambiguously back-extract the position of the traps and we suggest a correlation method to circumvent the `uniqueness´ problem.