Acceleration of an FPGA router

Author

Chan, Pak K. ; Schlag, Martine D F

Author_Institution

Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

fYear

1997

fDate

16-18 Apr 1997

Firstpage

175

Lastpage

181

Abstract

The authors describe their experience and progress in accelerating an FPGA router. Placement and routing is undoubtedly the most time-consuming process in automatic chip design or configuring programmable logic devices as reconfigurable computing elements. Their goal is to accelerate routing of FPGAs by 10 fold with a combination of processor clusters and hardware acceleration. Coarse-grain parallelism is exploited by having several processors route separate groups of nets in parallel. A hardware accelerator is presented which exploits the fine-grain parallelism in routing individual nets

Keywords

field programmable gate arrays; network routing; parallel algorithms; reconfigurable architectures; FPGA router acceleration; automatic chip design; coarse-grain parallelism; fine-grain parallelism; hardware acceleration; placement; processor clusters; programmable logic device configuration; reconfigurable computing elements; routing; Acceleration; Chip scale packaging; Costs; Field programmable gate arrays; Hardware; Logic devices; Parallel processing; Programmable logic devices; Routing; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-8159-4

Type

conf

DOI

10.1109/FPGA.1997.624617

Filename

624617