• DocumentCode
    2697362
  • Title

    Performances of a 16 K SRAM processed in a 150 nm SIMOX film for high speed applications

  • Author

    Auberton-Herve, A.J. ; Giffard, B. ; Bruel, M.

  • Author_Institution
    CEA-IRDI-D LETI CENG, Grenoble, France
  • fYear
    1989
  • fDate
    3-5 Oct 1989
  • Firstpage
    169
  • Lastpage
    170
  • Abstract
    Summaary form only given. A 16 K SRAM processed in a SIMOX thin SOI layer obtained with 1300°C furnace annealing without epitaxy is discussed. Address access time as low as 6 ns at 77 K have been obtained. The silicon under the gate is 150 nm thick. The design was optimized for bulk technology. For comparison, the circuits has been processed using a conventional 1.2 μm bulk CMOS technology. For a 5 V power voltage and a temperature of 300 K the address access time is 10-12 ns on SOI and 16-18 ns for bulk. For 1 MHz the active current is 43 nA on SOI and 45 mA on bulk. The study has shown that it is possible to process a bulk design on SOI without major changes. The yield is about 70% by using redundancy and 30% as prime yield. Thus, the use of thin SIMOX film instead of epitaxial layer on SIMOX reduces the cost without reducing the yield
  • Keywords
    CMOS integrated circuits; annealing; integrated memory circuits; ion implantation; random-access storage; semiconductor-insulator boundaries; 1 MHz; 10 to 12 ns; 1300 C; 150 nm; 16 kbit; 16 to 18 ns; 300 C; 43 nA; 6 ns; 65 nA; 66 K; SIMOX thin SOI layer; SRAM; Si; Si on insulator; address access time; bulk CMOS technology; furnace annealing; high speed applications; redundancy; separation by implantation of O; Annealing; CMOS process; CMOS technology; Circuits; Design optimization; Epitaxial growth; Furnaces; Random access memory; Silicon; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOS/SOI Technology Conference, 1989., 1989 IEEE
  • Conference_Location
    Stateline, NV
  • Type

    conf

  • DOI
    10.1109/SOI.1989.69817
  • Filename
    69817