Signal delay in distributed RC tree networks

The authors examine signal delay associated with distributed RC tree networks, and present an algorithm for computing distributed RC time constants. Skew measurements from a bipolar test chip utilizing various flip-flop loading configurations were used. The computer implementation of the algorithm used to check clock skew limits on a large bipolar ECL (emitter-coupled logic) gate array is also presented. On-chip clock skew, metal delays, and hold time margins are being analyzed and managed with this algorithm. The algorithm was implemented as an integral part of Tandem´s CAD-based VLSI physical design system and is part of the system-wide clock skew management methodology.<>