Signal delay in distributed RC tree networks

Author

Chengson, D. ; Frazao, C. ; Wang, H.W. ; Billett, B.

Author_Institution

Tandem Comput. Inc., Cupertino, CA, USA

fYear

1988

fDate

7-9 June 1988

Firstpage

2835

Abstract

The authors examine signal delay associated with distributed RC tree networks, and present an algorithm for computing distributed RC time constants. Skew measurements from a bipolar test chip utilizing various flip-flop loading configurations were used. The computer implementation of the algorithm used to check clock skew limits on a large bipolar ECL (emitter-coupled logic) gate array is also presented. On-chip clock skew, metal delays, and hold time margins are being analyzed and managed with this algorithm. The algorithm was implemented as an integral part of Tandem´s CAD-based VLSI physical design system and is part of the system-wide clock skew management methodology.<>

Keywords

VLSI; circuit CAD; delays; distributed parameter networks; linear network analysis; logic CAD; CAD-based VLSI physical design system; Tandem; bipolar ECL gate array; clock skew limits; computer implementation; distributed RC tree networks; emitter-coupled logic; flip-flop loading configurations; hold time margins; logic design; metal delays; system-wide clock skew management methodology; time constants; Algorithm design and analysis; Clocks; Computer networks; Delay effects; Distributed computing; Flip-flops; Logic arrays; Logic gates; Semiconductor device measurement; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15529

Filename

15529