Effect of pre-existing void in sub-30nm Cu interconnect reliability

Pre-existing void effect during electromigration in a sub-30nm wide Cu interconnect was observed. Two types of void are intentionally produced in a single damascene interconnect: 1) A void between Cu and capping dielectric layer (center void) is mainly produced from an excessive overhang by depositing a thick seed layer. 2) A void between Cu and barrier metal (side void) is produced from depositing a thin, discontinuous seed layer. Bi-modality was observed in center voided samples. 44% of lines with center voids show stiff resistance rises at high current density and most of them failed shortly after the resistance rise. No stiff resistance rise was observed at lower current density up to 3000 A.U. In side voided samples, no early failures was observed and the failure show no bimodal trend. Change in local current density around the void is expected to be the major factor for the electromigration performance difference between lines with center and side voids. We were able to show that shape and location of the pre-existing void have a significant effect on the reliability of Cu interconnect, and also the void behavior is highly sensitive to current density.