Design of ΣΔ modulators using FGMOS transistors

This paper presents the design of a second order continuous time low power and low voltage oversampling ΣΔ Modulator. This shows inside a comparator and an integrator with FGMOS techniques to facilitate the design and improve its characteristic behavior. The FGMOS transistor is simultaneously used in order to simplify the topology, accurately compensate for gain losses in the integrator and several nonidealities in the comparator; increase the dynamic range; reduce distortion; shift signal levels according to the specific requirements of individual devices; implement an easy common-mode sensing and feedback strategy; and tune the loop filter and reset the comparator. The ΣΔ Modulator operates with 2 kHz of band with 2V and consumes just 7.5μW of power. The simulation results are according to theoretical analysis.