An advanced four level interconnect enhancement module for 0.9 micron CMOS

A four-level metal interconnect enhancement has been developed for the AT&T Twin-Tub(V) 0.9-μm CMOS technology. The interconnect process includes resist etchback planarization at all dielectric levels, tungsten plugs for window fill, and a bilayer metal structure of Al-Cu/Ti:W for interconnection. The design rules include frameless contacts, stacked windows, and the maintenance of constant design rules throughout all four levels. Process details are described and electrical results are presented on the four-level metal enhancement. Electrical results include isolation, continuity, contact resistance, junction leakage, and transistor aging. The 0.9-μm CMOS n-channel and p-channel transistors exhibit no changes in parametric behavior due to the four-level metal interconnect process. Using the four-level interconnect enhancement results in a reduction of active chip area of up to 40% in AT&T´s 0.9-μm standard-cell ASIC technology