DocumentCode :
2698279
Title :
Source/drain area shrinkage using a novel contact and interconnect technology for CMOS application
Author :
Yoshida, Takehito ; Ogawa, Shin-ichi
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
fYear :
1990
fDate :
12-13 Jun 1990
Firstpage :
35
Lastpage :
41
Abstract :
A novel small source/drain (S/D) contact (SSDC) formation technology has been developed. In the SSDC structure, self-aligned contacts to small S/D regions can be formed without any contact holes, because a local TiSi2 interconnect on the isolation fields is directly connected with the lining of the S/D regions. In the SSDC process, the local TiSi2 interconnects were formed from the reaction of a sputter deposited amorphous-Si/Ti bilayer. The local TiSi 2 interconnect is thermally stable up to 900°C furnace annealing. This self-aligned contact structure combined with TiSi2 interconnect can realize a small S/D area which can bring about a new multilevel interconnect scheme for 0.5-μm ULSIs
Keywords :
CMOS integrated circuits; VLSI; contact resistance; integrated circuit technology; metallisation; titanium compounds; 0.5 micron; 900 degC; CMOS; ULSIs; furnace annealing; interconnect resistance; interconnect technology; isolation fields; local TiSi2 interconnects; multilevel interconnect scheme; self-aligned contacts; small source/drain contact formation technology; source/drain area shrinkage; sputter deposited amorphous Si-Ti bilayer; thermal stability; Annealing; CMOS technology; Fabrication; Integrated circuit interconnections; Silicides; Sputter etching; Surface contamination; Surface morphology; Titanium; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE
Conference_Location :
Santa Clara, CA
Type :
conf
DOI :
10.1109/VMIC.1990.127840
Filename :
127840
Link To Document :
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