Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays

This paper presents a detailed experimental investigation of the cycling-induced threshold voltage instability of deca-nanometer NAND Flash arrays, focusing on its dependence on cycling time and temperature. When the array is brought to a programmed state after cycling, instability mainly shows up as a negative shift of its threshold voltage cumulative distribution, increasing with time and resulting from partial recovery of cell damage created in the previous cycling period. The threshold voltage loss displays a strong dependence not only on the tunnel oxide electric field during retention, but also on the cycling conditions. In particular, performing cycling over a longer time interval or at higher temperatures delays the threshold voltage transients on the logarithmic time axis. The delay factor is studied as a function of the cycling duration and temperature on 60 and 41 nm technologies, extracting the parameter values required for a universal damage-recovery metric for NAND.