New scaling limitation of the floating gate cell in NAND Flash Memory

As the scaling in NAND Flash Memory is progressed, the various interferences among the adjacent cells are more and more increased and the new phenomenon which is ignored until now has to be considered. In this paper, we will introduce the new program interference phenomenon which is generated between the program word line and the adjacent word lines along the bit-line. This new program interference is that the Vth´s of the adjacent word lines along the bit-line are decreased while a word line is programming. Because this phenomenon is severely aggravated as the gate space is decreased, we have to consider this program interference for the future technology nodes.