A simple electrical method for etch bias and process reliability determination

Author

Yiang, Kok-Yong ; Chin, Melida ; Marathe, Amit ; Aubel, Oliver

Author_Institution

Technol. Reliability Dev., GLOBALFOUNDRIES Inc., Sunnyvale, CA, USA

fYear

2010

fDate

2-6 May 2010

Firstpage

562

Lastpage

565

Abstract

A fast and simple electrical method is developed to characterize the etch bias and post-patterned ILD breakdown strength of back-end-of-line (BEOL) interconnects, as well as the middle-of-line (MOL) contact/poly module. The method provides a timely and valuable monitoring mechanism for assessing lithography, etch, thin-film quality and process reliability windows.

Keywords

CMOS integrated circuits; electric breakdown; etching; integrated circuit interconnections; integrated circuit reliability; lithography; CMOS technology; back-end-of-line interconnects; etch bias electrical method; intralevel dielectric breakdown; lithography; middle-of-line contact-poly module; post-patterned ILD breakdown strength; process reliability determination; process reliability windows; thin-film quality; CMOS technology; Chemical technology; Dielectric breakdown; Electric breakdown; Etching; Lithography; Monitoring; Reliability engineering; Samarium; Testing; Etch bias; VRDB; line-edge roughness (LER);

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2010 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-5430-3

Type

conf

DOI

10.1109/IRPS.2010.5488771

Filename

5488771