Comparison of two calibration methods for a package stress measurement testchip

Analog and digital ICs are built up with bipolar or MOS (Metal Oxide Semiconductor) transistors. Such miniaturized transistor structures can fail when the thermo-mechanical stress becomes critical. The main aim of this work is to analyze the thermo-mechanical stress in integrated devices. Different approaches have been proposed to determine the thermo-mechanical stress effect in an IC device, based on stress-dependent properties of resistors, bipolar transistors or MOS transistors. In this paper two calibration methods for stress sensitive on-chip CMOS transistors are presented. One benefit of the described structures is that they can be produced in a standard semiconductor process. Another benefit is that electrical parameters of compact MOS transistors, in particular their charge carrier mobility, are highly stress dependent. The reliability of the presented calibration methods is verified by measurements and simulations.