Title :
SEE test and modeling results on 45nm SRAMs with different well strategies
Author :
Gasiot, Gilles ; Uznanski, Slawosz ; Roche, Philippe
Author_Institution :
Technol. R&D/Central CAD & Design Solutions, STMicroelectronics, Crolles, France
Abstract :
This paper presents heavy ion experimental results on SRAMs processed with 45nm bulk technology. Experiments were analyzed for Multiple Cells Upset (MCU) occurrence. The tested device was especially designed for MCU studies. In order to limit their spread it embeds different well strategies: usage of triple well layer and several densities of well ties.
Keywords :
SRAM chips; semiconductor device models; semiconductor device testing; MCU studies; SEE modeling; SEE test; SRAM; heavy ion experimental results; multiple cells upset; size 45 nm; triple well layer; CMOS technology; Design automation; Error correction codes; Frequency; Paper technology; Random access memory; Research and development; Space technology; Testing; Voltage; Multiple Cell Upsets; heavy ions; triple well; well engineering;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-5430-3
DOI :
10.1109/IRPS.2010.5488794
