Mechanism of high-k dielectric-induced breakdown of the interfacial SiO2 layer

Author

Bersuker, G. ; Heh, D. ; Young, C.D. ; Morassi, L. ; Padovani, A. ; Larcher, L. ; Yew, K.S. ; Ong, Y.C. ; Ang, D.S. ; Pey, K.L. ; Taylor, W.

Author_Institution

SEMATECH, Austin, TX, USA

fYear

2010

fDate

2-6 May 2010

Firstpage

373

Lastpage

378

Abstract

A mechanism of degradation and breakdown in high-k/metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO₂ layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing SILC temperature dependency and its exponential increase from the fresh through soft and progressive breakdown phases.

Keywords

MOSFET; high-k dielectric thin films; interface states; semiconductor device breakdown; semiconductor device models; semiconductor device reliability; silicon compounds; SILC temperature; SiO₂; grain boundaries; high-k dielectric-induced breakdown; interfacial layer; metal-gate transistors; oxygen-deficient filament; progressive breakdown phases; semiconductor device electrical test; semiconductor device modeling; semiconductor device physical analysis; Degradation; Dielectric breakdown; Electric breakdown; Electron traps; Grain boundaries; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Stress measurement; Testing; breakdown; high-k dielectrics; interfacial layer;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2010 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-5430-3

Type

conf

DOI

10.1109/IRPS.2010.5488800

Filename

5488800