DocumentCode
2699178
Title
High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path
Author
Ribes, G. ; Mora, P. ; Monsieur, F. ; Rafik, M. ; Guarin, F. ; Yang, G. ; Roy, D. ; Chang, W.L. ; Stathis, J.
Author_Institution
STMicroelectronics, Hopewell Junction, NY, USA
fYear
2010
fDate
2-6 May 2010
Firstpage
364
Lastpage
368
Abstract
We show that a model in which the breakdown of the interfacial layer induces a correlated breakdown in the high-K, at the same location, provides a good model of the high-K/IL gate stack statistics. We discuss of the implication of this model on the lifetime projection.
Keywords
CMOS integrated circuits; electric breakdown; high-k dielectric thin films; integrated circuit modelling; integrated circuit reliability; CMOS integrated circuits; High-K gate stack breakdown statistics model; correlated interfacial layer; high-k breakdown path; lifetime projection; CMOS technology; Dielectric breakdown; Electric breakdown; Electronic mail; Foundries; High K dielectric materials; High-K gate dielectrics; Semiconductor device modeling; Statistics; Voltage; CMOS; High-K metal gate dielectrics; breakdown; reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location
Anaheim, CA
ISSN
1541-7026
Print_ISBN
978-1-4244-5430-3
Type
conf
DOI
10.1109/IRPS.2010.5488802
Filename
5488802
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