Title :
SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET
Author :
Uemura, Taiki ; Tosaka, Yoshiharu ; Matsuyama, Hideya ; Shono, Ken ; Uchibori, Chihiro J. ; Takahisa, Keiji ; Fukuda, Mitsuhiro ; Hatanaka, Kichiji
Author_Institution :
Fujitsu Microelectron. Ltd., Kuwana, Japan
Abstract :
We have developed a robust latch for achieving high reliability in LSI. The latch can attenuate multi-node single-event-upset (MNSEU) and single event transient on local-clock (SETLC). The robust latch has Dual-clock-buffers (DCB) and Double-height-cell (DHC) technologies. Results on neutron acceleration experiments show that DHC can dramatically attenuate MNSEU and DCB can protect almost SETLC of the latch. In addition, we investigate optimum design in well structure.
Keywords :
error correction codes; integrated circuit reliability; large scale integration; DCB technology; DHC technology; LSI reliability; MNSEU; SEILA; SETILC; double-height-cell technology; dual-clock-buffers technology; error correction codes; local-clock-SET mitigation; multinode single event-upset; multinode-SEU mitigation; neutron acceleration experiments; single event transient on local-clock; soft error immune latch; Acceleration; Clocks; DH-HEMTs; Error correction codes; Large scale integration; Latches; Neutrons; Protection; Robustness; Testing; MNSEU; SET; SETLC; SEU; charge sharing; local-clock; soft-error;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2010 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-5430-3
DOI :
10.1109/IRPS.2010.5488827
