LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design

This paper presents a new layout design principle called LEAP which is an acronym for Layout Design through Error-Aware Transistor Positioning. This principle extends beyond traditional layout techniques, such as node separation, and significantly improves the soft error resilience of digital circuits with negligible performance cost. In this study, we applied the LEAP technique to the Dual Interlocked Storage Cell (DICE) and designed a new sequential element called LEAP-DICE. This element retains the circuit topology and transistor sizing of DICE but has a new layout based on the LEAP principle. Radiation experiments using an 180nm CMOS test chip demonstrate that our LEAP-DICE flip-flop encounters 5X fewer errors on average compared to our reference DICE flip-flop, and 2,000X fewer errors on average compared to a conventional D-flip-flop. Our LEAP-DICE flip-flop imposes negligible power and delay costs and 40% flip-flop-level area costs compared to our reference DICE flip-flop.