Mature processability and manufacturability by characterizing VT and Vmin behaviors induced by NBTI and AHTOL test

A systematical reliability assessment for technology process that is essential for technology feasibility and qualification is presented by addressing physical and electrical characterization and reliability evaluation. By varying the duty cycle of enhanced pulsed radio frequency (eprf) technique used for the gate oxynitridation, the effects of nitrogen concentration and profile at SiO₂/Si interface on V_T and V_min shift of thin oxide pMOSFET (~20A) and SRAM, which result from negative bias temperature stability (NBTI) and accelerated high temperature operating life (AHTOL) stress test, are meticulously investigated. Using secondary ion mass spectrometry (SIMS) and high resolution Rutherford back scattering (H-RBS), nitrogen concentration and profile at the interface are carefully characterized. It is found that pMOSFET device processed with 10% of eprf provides ~2× longer NBTI lifetimes than with 20% of eprf due to lower nitrogen concentration at the interface. Furthermore, V_min shift of SRAM with 10% of eprf, which is caused by AHTOL test conditioned at 140°C with 1.4× V_dd, is ~3~4× less than with 20% of eprf. In fact, a nano-probing technique elucidates that Vmin shift is mainly attributed to the mismatch of V_T between pull-up (PU) transistors in SRAM induced by NBTI stemmed from AHTOL test. It is also empirically shown that V_min shift behavior is in good agreement with the read margin rather than the write. Accordingly, a stabilized V_min drift behavior consistently adheres to the write margin. Hence, the optimization of interfacial nitrogen concentration results in less pMOSFET NBTI degradation so as to efficiently suppress V_min shift of SRAM. Besides, increasing PU transistor size that decreases the γ value (the ratio of I_on current of PG to PU) can also reduce V_min shift during AHTOL test. Finally, matu- - re processability and manufacturability are attained by characterizing V_T and V_min behaviors for pMOSFET and SRAM from the front-end-of-line (FEOL) process optimization and SRAM bit-cell design aspect.