Off state incorporation into the 3 energy mode device lifetime modeling for advanced 40nm CMOS node

Author

Bravaix, A. ; Guérin, C. ; Goguenheim, D. ; Huard, V. ; Roy, D. ; Besset, C. ; Renard, S. ; Randriamihaja, Y. Mamy ; Vincent, E.

Author_Institution

Maison des Technol., ISEN-IM2NP, Toulon, France

fYear

2010

fDate

2-6 May 2010

Firstpage

55

Lastpage

64

Abstract

Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been done on the distinct impact of the measuring bias and stressing conditions in Sub-V_T regime. The latter can be much more degraded than On-state parameters showing the amphoteric nature of Si-H bonds breaking rates throughout the channel-GDO. Off-mode damage has been included in the 3 mode energy device lifetime giving a useful modeling for any AC waveforms suitable for digital to analog operations.

Keywords

CMOS integrated circuits; hot carriers; silicon; AC waveforms; CMOS node; PMOSFET; channel-GDO; digital-analog operations; energy mode device lifetime modeling; gate-drain overlap; hot-carrier degradation; localized charge trapping; off state incorporation; size 40 nm; spacer oxide; Degradation; Electron traps; Energy consumption; Hot carriers; MOSFET circuits; Niobium compounds; Semiconductor device modeling; Stress measurement; Temperature; Titanium compounds; Band to Band Tunneling; Cold Carriers; Gate-Induced Drain Leakage; High Temperature; Hot Carriers; Interface traps; Multi Vibrational Excitation; Off Mode; Oxide traps;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2010 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-5430-3

Type

conf

DOI

10.1109/IRPS.2010.5488852

Filename

5488852