Title :
An approach to high-level synthesis system validation using formally verified transformations
Author :
Radhakrishnan, Rajesh ; Teica, Elena ; Vermuri, R.
Author_Institution :
Cincinnati Univ., OH, USA
Abstract :
Complexity of advanced high-level synthesis algorithms can be attributed to design quality concerns. However this complexity may lead to software errors in their implementations which may adversely impact design correctness. Transformational synthesis is a synthesis methodology where localized, behavior-preserving register transfer level (RTL) transformations are used to obtain a correct and constraint satisfying RTL design. This paper presents the novel use of a set of such transformations in validating an existing non-transformational synthesis system by discovering and to some extent isolating software errors
Keywords :
formal verification; high level synthesis; logic design; behavior-preserving register transfer level transformations; design correctness; formally verified transformations; high-level synthesis system validation; software errors; transformational synthesis; Algorithm design and analysis; Error correction; Formal verification; High level synthesis; Software algorithms; Software tools;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2000. Proceedings. IEEE International
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-0786-7
DOI :
10.1109/HLDVT.2000.889564
