Title :
Refining abstract equivalence analysis for embedded system design
Author :
Hsieh, Henry ; Balarin, F.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA
Abstract :
The synchronous assumption has made it possible to develop efficient procedures for establishing functional equivalence between different implementations in the domains of synchronous circuits and synchronous reactive systems. This notion is extended to embedded systems that do not satisfy the synchronous assumption inside their boundaries but only at the interface with the environment. Efficient, but conservative, synchronous equivalence analysis algorithms have been developed. In this work, we propose extensions to these algorithms that allow trading off the complexity with the conservativeness of the results
Keywords :
equivalence classes; finite state machines; logic design; abstract equivalence analysis; complexity; embedded system design; equivalence analysis; functional equivalence; synchronous circuits; synchronous reactive systems; Algorithm design and analysis; Automata; Circuit synthesis; Context; Electronic mail; Embedded system; Laboratories; Network synthesis; Processor scheduling; Space exploration;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2000. Proceedings. IEEE International
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-0786-7
DOI :
10.1109/HLDVT.2000.889575
