Title :
Investigations of Cu bond structures and demonstration of a wafer-level 3D integration scheme with W TSVs
Author :
Chen, K.N. ; Cabral, C. ; Lee, S.H. ; Andry, P.S. ; Lu, J.-Q.
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Evaluations of two Cu bond structures, oxide-recessed and lock-n-key, are reported. In addition to excellent electrical characteristics of bonded via chain, alignment tests show lock-n-key bond structures have better performance than oxide-recessed ones. Finally a wafer-level three-dimensional (3D) integration scheme using lock-n-key Cu bond structure with W TSV is demonstrated.
Keywords :
copper; three-dimensional integrated circuits; wafer bonding; Cu; TSV; lock-n-key bond structures; oxide-recessed bond structure; wafer-level three-dimensional integration scheme; Bonding forces; Educational institutions; Electric variables; Etching; Polymers; Research and development; Temperature; Testing; Through-silicon vias; Wafer bonding; 3D; Cu bonding; Oxide-recess and Lock-n-key;
Conference_Titel :
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-5063-3
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2010.5488904
