DocumentCode :
2700561
Title :
Wafer-on-wafer (WOW) stacking with damascene-contact TSV for 3D integration
Author :
Maeda, Nobuhide ; Kitada, Hideki ; Fujimoto, Koji ; Suzuki, Kousuke ; Nakamura, Tomoji ; Kawai, Akihito ; Arai, Kazuhisa ; Ohba, Takayuki
Author_Institution :
Sch. of Eng., Univ. of Tokyo, Tokyo, Japan
fYear :
2010
fDate :
26-28 April 2010
Firstpage :
158
Lastpage :
159
Abstract :
Through-silicon via (TSV) module-process based on wafer-on-wafer (WOW) stacking has been developed. Stacking wafers were thinned down to 20 μm, and TSVs with a diameter of 30 μm were fabricated to connect inter-wafers without electrical failure in chain TSV interconnects. The TSVs were constructed with the damascene technique. Multi-wafer stacking was realized by planarizing TSV-heads with a diamond bit of a surface planer. A wafer bonding process was optimized to suppress void formation and alignment shift after adhesive cure. According to our simulation, thinner wafers and a thinner adhesive layer create less stress on a device under the TSV.
Keywords :
adhesive bonding; stacking; three-dimensional integrated circuits; wafer bonding; 3D integration; adhesive cure; alignment shift; damascene-contact TSV; multiwafer stacking; size 30 mum; through-silicon via module-process; void formation; wafer-on-wafer stacking; Bonding processes; Electric resistance; Glass; Sputter etching; Stacking; Tensile stress; Three-dimensional integrated circuits; Through-silicon vias; Viscosity; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on
Conference_Location :
Hsinchu
ISSN :
1524-766X
Print_ISBN :
978-1-4244-5063-3
Electronic_ISBN :
1524-766X
Type :
conf
DOI :
10.1109/VTSA.2010.5488906
Filename :
5488906
Link To Document :
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