Demonstration of a high performance 40-nm-gate carbon nanotube field-effect transistor

Carbon nanotubes (CNTs) are promising candidates for post-Si nanoelectronics (Avouris et al., 2003). They are particularly attractive for high-speed applications due to their ballistic properties and high Fermi velocity (~10⁶ m/s) Liang et al., 2001. The small-signal switching speed of a transistor is determined by the intrinsic delay time tau = 2piC_G/g_m, where C _G is the gate capacitance and g_m=dI_d/dV _gs is the transconductance. For carbon nanotube field-effect transistors (CNFETs), the highest g_m reported so far is ~ 27 muS by Javey et al. (Javey et al., 2004) using a dielectric film of 8-nm HfO₂ (K=15). In their CNFET, the gate capacitance per unit length is estimated to be C_G/L=1.8times10^-16 F/mum, resulting in a gate delay per unit length of dL=42 ps/mum. Here we present a high-performance CNFET with a delay time per unit length of dL=22 ps/mum, the smallest value reported for CNFETs to date. In order to further minimize the parasitic capacitances and lower the intrinsic gate capacitance, we utilize a dual-gate design and fabricate a 40-nm gate CNFET possessing excellent subthreshold and output characteristics, which is the shortest gate length for a well-tempered CNFET demonstrated so far