Title :
Investigations of performance enhancement in a poly-Si nanowire FET featuring independent double-gated configuration and its nonvolatile memory applications
Author :
Chen, Wei-Chen ; Hsu, Hsing-Hui ; Chang, Yu-Chia ; Lin, Horng-Chih ; Huang, Tiao-Yuan
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Charge-trapping SONOS devices featuring nanowire (NW) and independent double-gated (IDG) structure are fabricated and characterized. The mechanism leading to DG output current performance enhancement is investigated. Taking advantage of the separated-gated property, the back-gate bias effect is used to probe its impacts on programming efficiency. It is also discovered that reduced NW thickness leads to stronger back-gate effects.
Keywords :
elemental semiconductors; field effect transistors; flash memories; nanoelectronics; random-access storage; silicon; DG output current performance enhancement; Si; back-gate bias effect; charge-trapping SONOS devices; independent double-gated structure; nonvolatile memory; polySi nanowire FET; Controllability; Double-gate FETs; Electrons; Fabrication; Laboratories; Nanoscale devices; Nonvolatile memory; SONOS devices; Textile industry; Tunneling;
Conference_Titel :
VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-5063-3
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2010.5488911
