An ECL/BiCMOS multi-port RAM for high performance VLSI

The authors describe a multiport BiCMOS memory using both bipolar and MOS transistors in the cell. A special cell select line structure is used which utilizes ECL (emitter coupled logic) voltage levels for read access. This memory cell is much smaller and less power consuming than an ECL multiport RAM cell, and is therefore capable of a much higher performance and larger integration. The cell has a smaller size and fewer components than a pure bipolar memory cell with the same functionality. Since the entire read path is composed of ECL circuits, a read access time comparable with ECL RAMs is achieved. The memory cell´s power dissipation is comparable to that of a pure CMOS RAM cell