Key sub 1nm EOT CMOS enabler by comprehensive PMOS design

Author

Tseng, J. ; Ragnarsson, L.-A. ; Schram, T. ; Akheyar, A. ; Okuno, Y. ; Li, Z.L. ; Aoulaiche, M. ; Rohr, E. ; Witters, T. ; Adelmann, C. ; Delabie, A. ; Paraschiv, V. ; Kerner, C. ; Xiong, K. ; Mueller, M. ; Hoffmann, T. ; Absil, P. ; Biesemans, S.

Author_Institution

TSMC, Leuven, Belgium

fYear

2010

fDate

26-28 April 2010

Firstpage

116

Lastpage

117

Abstract

A high performance CMOS HK/MG sub 1nm EOT solution is demonstrated. The drive currents at Ioff = 100 nA/μm with VDD = 1 V are 1.25 mA/μm and 0.56 mA/μm for n and pMOS respectively without strain boost. Through a novel process integration design, PMOS EWF roll-off and NBTI problems with EOT scaling are overcome until sub 1nm EOT region. The PMOS -0.25V Vt @1um Lg and NBTI 10 years life time @0.7V overdrive are thus offered with 0.94nm EOT. Mechanisms and guidelines for solving theses issues are provided after a comprehensive study here. These concepts are beneficial to either gate-first or gate-last approach with EOT scaling.

Keywords

MOS integrated circuits; semiconductor device reliability; EOT CMOS enabler; comprehensive PMOS design; Annealing; CMOS technology; Capacitive sensors; Degradation; Guidelines; Hafnium oxide; High-K gate dielectrics; Niobium compounds; Process design; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-5063-3

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2010.5488923

Filename

5488923