Title :
Performance Comparison Between Bulk and SOI Junctionless Transistors
Author :
Ming-Hung Han ; Chun-Yen Chang ; Hung-Bin Chen ; Jia-Jiun Wu ; Ya-Chi Cheng ; Yung-Chun Wu
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable on/offcurrent ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an on/offcurrent ratio of 105 at W = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage Vth of the JL bulk FinFET can be easily tuned by varying substrate doping concentration Nsub. The modulation range of Vth as Nsub changes from 1018 to 1019 cm-3, which is around 30%.
Keywords :
MOSFET; nanowires; semiconductor device models; silicon-on-insulator; 3D quantum transport device simulation; SOI junctionless transistors; channel/substrate junction; drain-induced barrier; effective channel thickness; junctionless bulk FinFET; short-channel characteristics; silicon-on-insulator JL nanowire transistor; substrate doping concentration; subthreshold slope; threshold voltage; Doping; FinFETs; Logic gates; Mathematical model; Semiconductor process modeling; Substrates; 3-D simulation; Fin-shaped field-effect transistor (FinFET); junctionless (JL);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2012.2231395
