Power, cost and circuit IP reuse: The real limiter to Moore´s Law over the next 10 years

Author

Thompson, Scott E.

Author_Institution

Univ. of Florida, Gainesville, FL, USA

fYear

2010

fDate

26-28 April 2010

Firstpage

88

Lastpage

89

Abstract

Long ago predicted limits for the planar CMOS structure, Silicon (Si) materials, and optical lithography are now present and being addressed in present day 32 and 28 nm technology logic nodes. However, as the market emphasis shifts from high performance computing to consumer mobile in the race to produce the next 15 billion intelligent, connected devices by 2015, new issues such as extreme low power constraints and low cost have now became a priority as the industry has hit a power supply "1V Wall" for logic technologies. This paper looks at the logic technology roadmap for the next 10 years with a new perspective. With power, cost, and System On a Chip (SOC) being the present day industry market drivers, do many of the projects started ~30 years ago to address scaling and fundamental limits to Si planar CMOS (e.g. Multigate MOSFETs, III-V materials, etc), still make sense today?

Keywords

CMOS logic circuits; elemental semiconductors; industrial property; low-power electronics; silicon; system-on-chip; Moore law; Si; circuit IP reuse; extreme low power constraints; high performance computing; logic nodes; logic technology roadmap; optical lithography; planar CMOS structure; size 28 nm; size 32 nm; system on a chip; voltage 1 V; CMOS logic circuits; CMOS technology; Costs; Electricity supply industry; III-V semiconductor materials; Logic devices; Moore´s Law; Optical materials; Optical sensors; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-5063-3

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2010.5488936

Filename

5488936