• DocumentCode
    2701186
  • Title

    Issues associated with the use of electroless copper films for submicron multilevel interconnections

  • Author

    Thomas, Michael E. ; Sekigahama, Satoshi ; Myers, Sharon A.

  • Author_Institution
    Nat. Semicond. Corp., Santa Clara, CA, USA
  • fYear
    1990
  • fDate
    12-13 Jun 1990
  • Firstpage
    335
  • Lastpage
    337
  • Abstract
    Cu films between 1000 Å and 1 μm thick were deposited from an electroless Cu plating bath on various metal seed layers. The bulk resistivity of Cu films was a function of the film thickness. For thin films of 1000 Å, the electrical resistivity was three times greater than reported bulk values. For 1-μm films, resistivities of 2.3 μΩ-cm were obtained. This larger resistivity is apparently influenced by defects grown into the film. The electrical and physical properties of these films were examined after rapid thermal processing at temperatures of up to 900°C on inert substrates. Transmission electron microscope (TEM) analyses indicated changes in grain size from 600 Å to 2500 Å. Thin layers of FCC metals in contact with Cu, such as Ni or Pt, were detrimental to the electrical resistivity after moderate thermal processing. These interactions could be easily predicted from phase diagrams of Cu with other FCC metals and indicate that Ni encapsulation of Cu is impractical. Selective Cu deposition into dielectric channels on seed layers was found to be clean with little if any random field nucleation. Copper that was selectively deposited into contacts of a test gate array exhibited electrical continuity on CVD W but showed contact resistances substantially larger than standard metallurgies
  • Keywords
    contact resistance; copper; electroless deposited coatings; electronic conduction in metallic thin films; large scale integration; metallisation; transmission electron microscope examination of materials; 1E-7 to 1E-6 m; 900 degC; TEM; bulk resistivity; contact resistances; dielectric channels; electroless plating bath; film thickness; gate array; grain size; metal seed layers; metallisation; phase diagrams; physical properties; rapid thermal processing; submicron multilevel interconnections; thermal processing; Conductivity; Contacts; Copper; Electric resistance; Electrons; FCC; Rapid thermal processing; Substrates; Temperature; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Multilevel Interconnection Conference, 1990. Proceedings., Seventh International IEEE
  • Conference_Location
    Santa Clara, CA
  • Type

    conf

  • DOI
    10.1109/VMIC.1990.127889
  • Filename
    127889