An experimental 220 MHz 1 Gb DRAM

Author

Horiguchi, M. ; Sakata, Tsuyoshi ; Sekiguchi, Takeshi ; Ueda, Shuichi ; Tanaka, Hiroya ; Yamasaki, E. ; Nakagome, Y. ; Aoki, Masaki ; Kaga, I. ; Ohkura, Michiko ; Nagai, R. ; Murai, F. ; Tanaka, T. ; Iijima, S. ; Yokoyama, Naoki ; Gotoh, Yusuke ; Shoji, K

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

252

Lastpage

253

Abstract

With the arrival of the multimedia era, high-data-rate memory LSIs are becoming increasingly important to keep up with high-speed CPUs, graphics processors, and other consumers of stored data. Video editing and replaying of high-definition television in particular require a high bandwidth. This paper presents two circuit technologies for a synchronously operating high-data-rate 1 Gb DRAM: a distributed-column-control architecture reducing the burst-mode cycle time, and a ringing-canceling output buffer ensuring reliable high-speed data transfer.

Keywords

DRAM chips; large scale integration; 1 Gbit; 220 MHz; LSI; burst-mode cycle time; circuit technologies; distributed-column-control architecture; high-speed data transfer; ringing-canceling output buffer; synchronous DRAM; Centralized control; Circuits; Clocks; Data engineering; Delay effects; Latches; Random access memory; Signal generators; Timing; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535544

Filename

535544