Maximizing transient availability of real-time Onboard Reconfigurable Processing Platforms: An analytical redundancy inspired approach

Onboard Reconfigurable Processing Platform (ORPP), which mainly consists of reconfigurable devices (FPGAs) and auxiliary co-processors such as DSPs, is dedicated to in-situ real-time computing for various space missions. Harsh ionizing radiation effects have been observed during flight thus make it crucial to design fault tolerance in ORPPs. Transient available refers to ORPP can mask transient faults such as Single Event Upset (SEU), Single Event Transient (SET) in their circuits therefore maintain the correctness as well as timeliness of its outputs. Redundancy at different levels is useful means to avoid transient faults and signal an error indicator for later fault recovery process. Among them the chip-level redundancy method is often regarded as coarse-grained and expensive in terms of area and cost. Whereas fine-grained redundancy approaches including Triple Module Redundancy (TMR) in FPGA suffer a lot in mapping user modules in diversity since adjacent placement of duplicated modules is lack of immunity to single particle induced multiple bits upset (MBU). We reviewed the chip-level method and propose an analytical redundancy inspired fault tolerant scheme which uses the spare computing resource of co-processors to generate two off-chip redundancy modules for majority voting in the voter. In contrast to the conventional hardware redundancy methods, the proposed approach takes the advantage of different radiation behaviors in FPGAs and DSPs, therefore has the maximum transient availability.