A fast-frequency-switching PLL synthesizer LSI with a numerical phase comparator

A synthesizer fabricated in a single chip requires 3 improvements: (1) new numerical phase comparator using a digital differential phase comparator (DDPC) that avoids frequency offset, (2) digital loop filter (DLF) that has notch frequency characteristics at the frequency step to suppress the DDPC noise, (3) interpolation using a /spl Sigma//spl Delta/ modulator must be used to implement a 20 b resolution digital-to-analog converter (DAC). The architecture of a PLL frequency synthesizer with numerical phase comparator, which satisfies these requirements, is described. The PLL frequency synthesizer, consists of the DDPC, DLF, /spl Sigma//spl Delta/ modulator, DAC, LPF (low pass filter), and VCO. The DDPC calculates the phase difference between the output of the VCO and the reference clock. The DLF filters out the DDPC noise. The output of the DLF is converted into an analog signal by the DAC and used to control the VCO. The PLL synthesizer LSI is in 0.6 /spl mu/m BiCMOS and the chip area is 5.69/spl times/5.51 mm/sup 2/. Total current is 20 mA, when the supply voltage is 4.5 V for the analog circuit and 3.3 V for the digital circuit. Switching time is <0.7 ms at a 16 MHz hopping frequency. No spurious components are observed and spurious level is <-75 dBc at a 25 kHz offset frequency due to the notch filter in the DLF.