An advanced 0.8 μm complementary BiCMOS technology for ultra-high speed circuit performance

Author

Burger, W.R. ; Lage, C. ; Landau, B. ; DeLong, M. ; Small, J.

Author_Institution

Nat. Semicond. Corp., Puyallup, WA, USA

fYear

1990

fDate

17-18 Sep 1990

Firstpage

78

Lastpage

81

Abstract

An 0.8-μm fully complementary BiCMOS (CBiCMOS) process has been developed which offers superior drive capability and low-voltage performance compared to standard BiCMOS technologies. The CBiCMOS process was developed by the successful integration of a high-performance, poly emitter vertical PNP (F_t=17 GHz, emitter coupled logic gate delay=65 ps) and CMOS transistors (CMOS gate delay=68 ps). A CBiCMOS push-pull ring oscillator has been fabricated with a gate delay of 250 ps for a 1-pF load; this is believed to be the fastest loaded ring gate delay ever reported for gate lengths down to 0.6 μm. This CBiCMOS technology is expected to play an important role in the development of future generations of high-speed memories (i.e., 4-Mbit emitter coupled logic I/O SRAMs and beyond) which will require novel process technologies to avoid the deleterious effects of reduced voltage operation

Keywords

BIMOS integrated circuits; VLSI; integrated circuit technology; 0.8 micron; 17 GHz; 250 ps; 65 ps; 68 ps; CBiCMOS push-pull ring oscillator; CMOS gate delay; CMOS transistors; complementary BiCMOS technology; drive capability; emitter coupled logic I/O SRAMs; emitter coupled logic gate delay; gate delay; high-speed memories; low-voltage performance; poly emitter vertical PNP transistors; ultra-high speed circuit; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Circuit optimization; Delay; Integrated circuit interconnections; Isolation technology; Low voltage; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1990., Proceedings of the 1990

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1990.171131

Filename

171131