Self-aligned shallow trench isolation recess effect on cell performance and reliability of 42nm NAND flash memory

Author

Liu, C.H. ; Lin, Y.M. ; Shirota, R. ; Wei, H.C. ; Kuo, L.T. ; Liu, C. Han ; Chen, S.H. ; Hwang, H.P. ; Sakamoto, Y. ; Pittikoun, S.

Author_Institution

Powerchip Semicond. Corp., Hsinchu, Taiwan

fYear

2010

fDate

26-28 April 2010

Firstpage

46

Lastpage

47

Abstract

Self-aligned shallow trench isolation recess effect on 42 nm node NAND flash to achieve high performance and good reliability has been studied and demonstrated. As cell STI recess is increased by 23 nm, 29% narrower cell Vth distribution width and 54% less cell Vth shift after 125°C, 2 hours can be obtained. Furthermore, the endurance window is obviously improved ~0.5V as the distance of the active area edge to control gate (CG) is increased at the same time. Deeper STI recess and enough active area edge to CG distance are a promising profile for floating gate based NAND flash at 42 nm node and beyond.

Keywords

NAND circuits; flash memories; integrated circuit reliability; NAND flash memory; cell performance; cell reliability; control gate; floating gate; self-aligned shallow trench isolation recess effect; size 42 nm; temperature 125 degC; time 2 hour; Character generation; Dielectric substrates; Dry etching; Hydrogen; Interference; Nonvolatile memory; Plasma applications; Threshold voltage; Voltage control; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-5063-3

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2010.5488956

Filename

5488956