Planar FDSOI technology for sub 22nm nodes

Author

Faynot, O. ; Andrieu, F. ; Fenouillet-Béranger, C. ; Weber, O. ; Perreau, P. ; Tosti, L. ; Brevard, L. ; Rozeau, O. ; Scheiblin, P. ; Thomas, O. ; Poiroux, T.

Author_Institution

MINATEC, CEA-LETI, Grenoble, France

fYear

2010

fDate

26-28 April 2010

Firstpage

26

Lastpage

27

Abstract

Recent device developments and achievements have shown that undoped channel planar Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 22nm node and below. This planar option seems to be even easier than non planar FinFET devices. This paper will report the main results obtained with this technology and will compare these results with the state of the art of Bulk and FinFET technologies: electrostatic performance, drivability, variability and scalability will be presented through silicon data and TCAD analysis. Challenges with respect to Multiple VT aspects and SRAM will also be reported.

Keywords

MOSFET; silicon-on-insulator; SRAM; TCAD analysis; bulk technology; electrostatic performance; multiple VT aspects; nonplanar FinFET devices; silicon on insulator; size 22 nm; undoped channel planar fully depleted SOI devices; CMOS technology; Data analysis; Degradation; Electrostatic analysis; FinFETs; Performance analysis; Random access memory; Scalability; Silicon on insulator technology; Strain control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-5063-3

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2010.5488963

Filename

5488963