Effective co-verification of IEEE 802.11a MAC/PHY combining emulation and simulation technology

This work presents a system architecture and effective co-verification methodologies for the IEEE 802.11a medium access control (MAC) layer/physical (PHY) layer implementation. The architecture modeling includes hardware/software partitioning of a total system based on timing measurements from the C/C++ and Verilog design, and analysis of real-time requirements specified in the standard. The system is built on an evaluation platform that contains a Xilinx Virtex-11 FPGA and an Altera Excalibur ARM922. The authors presented an approach that combines emulation and simulation for efficient debugging of the IEEE 802.11a wireless LAN using various verification technologies.