Title :
Re-hosting the operational flight program for a tactical fighter plane´s radar data processor: a software upgrade methodology
Author :
Murray, J.P. ; Cole, C.K. ; Warlick, E.S.
Author_Institution :
Avionics Dev. Branch, Georgia Tech. Res. Inst., Atlanta, GA, USA
Abstract :
As military budgets shrink, military contractors are under increasing pressure to produce high performance systems for the lowest possible cost. Upgrading a processor-based component of a defense system involves both hardware and software migration tasks. The software migration task typically requires the re-hosting of assembly-language programs from older complex instruction set computers (CISC) to the native code of the reduced instruction set computers (RISC) used in designs today. Two distinct phases can be identified in this re-hosting effort: the initial translation of the software, and the debugging of the resulting code. This paper discusses the software upgrade methodology used to re-host the operational flight program (OFF) of the fielded radar data processor (RDP) unit of a radar system aboard a tactical fighter plane. In particular, the paper concentrates on the streamlining and debugging processes used to re-host the previously translated OFF of the RDP onto a new hardware platform designed around the Intel i960 RISC microprocessor architecture. The initial translation of the software from its proprietary assembly language to i960 code has been previously described; this paper will discuss the techniques used to test and debug that translated code, as well as those techniques used to upgrade from that baseline code to a later release of the proprietary OFF. All of the debugging and verification was accomplished by a team of three full-time engineers in approximately one calendar year. The techniques described provide an effective software upgrade “attack plan” that can be applied to a vast number of aging systems
Keywords :
aerospace computing; aircraft computers; economics; military avionics; military computing; program debugging; program verification; radar applications; reduced instruction set computing; RISC; assembly-language programs; complex instruction set computers; cost-effectiveness; debugging; debugging processes; defense systems; high performance systems; military contractor; military-approved microprocessor chips; operational flight program; radar data processor; re-hosting; reduced instruction set computers; software migration; software upgrade methodology; streamlining and debugging processes; tactical fighter; translation of the software; useful live; verification; weapons; Assembly; Computer aided instruction; Computer architecture; Costs; Hardware; Microprocessors; Military computing; Radar; Reduced instruction set computing; Software debugging;
Conference_Titel :
Aerospace and Electronics Conference, 1996. NAECON 1996., Proceedings of the IEEE 1996 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-3306-3
DOI :
10.1109/NAECON.1996.517694