• DocumentCode
    2702271
  • Title

    Building fast bundled data circuits with a specialized standard cell library

  • Author

    Roine, T.

  • Author_Institution
    Dept. of Inf., Oslo Univ.
  • fYear
    1994
  • fDate
    3-5 Nov 1994
  • Firstpage
    134
  • Lastpage
    143
  • Abstract
    A method for building fast, optimized bundled data circuits from a specialized CMOS standard cell library is presented. The method has been successfully used for the design of a FIFO buffer for a multicomputer network. This chip, which contains about 19000 transistors in a 1.5 μm CMOS process, achieves a throughput of about 150 million symbols per second
  • Keywords
    asynchronous circuits; CMOS standard cell library; FIFO buffer; data circuits; fast bundled; multicomputer network; standard cell library; Asynchronous circuits; Circuit simulation; Delay; Informatics; Libraries; Logic circuits; Pipeline processing; Safety; Throughput; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Research in Asynchronous Circuits and Systems, 1994., Proceedings of the International Symposium on
  • Conference_Location
    Salt Lake City, UT
  • Print_ISBN
    0-8186-6210-7
  • Type

    conf

  • DOI
    10.1109/ASYNC.1994.656302
  • Filename
    656302
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2702271