Title :
Testing 3D chips containing through-silicon vias
Author :
Marinissen, Erik Jan ; Zorian, Yervant
Author_Institution :
IMEC vzw, Leuven, Belgium
Abstract :
Today´s miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D stacked ICs (3D-SICs) based on through-silicon vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.
Keywords :
design for testability; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; integrated circuit testing; three-dimensional integrated circuits; wafer level packaging; 3D chip testing; 3D stacked IC; high density integration; on-chip DFT; package level test; packaging technology; through silicon vias; wafer level test; wafer-level probe access; Cost function; Electronics industry; Integrated circuit interconnections; Integrated circuit packaging; Logic testing; Manufacturing processes; Marine technology; Power dissipation; Through-silicon vias; Wafer scale integration;
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
DOI :
10.1109/TEST.2009.5355573
