A radix-16 SRT division unit with speculation of the quotient digits

Author

Cornetta, Gianluca ; Cortadella, Jordi

Author_Institution

Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Barcelona, Spain

fYear

1999

fDate

4-6 Mar 1999

Firstpage

74

Lastpage

77

Abstract

The speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the quotient digit generation function. In this paper we present an analytical approach that extends the theory developed for standard SRT division and permits us to implement division schemes where a simpler function speculates the quotient digit. This leads to division units with shorter cycle time and variable latency since a speculation error may be produced and a post-correction of the quotient may be necessary. We have applied our algorithm to the design of a radix-16 speculative divider for double precision floating point numbers, that resulted in being faster than analogous implementations

Keywords

VLSI; dividing circuits; error correction; error detection; floating point arithmetic; integrated logic circuits; timing; cycle time reduction; digit-recurrence algorithm; double precision floating point numbers; post-correction; quotient digit generation function; quotient digits speculation; radix-16 SRT division unit; speculation error; speculative divider; variable latency; Computer architecture; Convergence; Costs; Delay; Error correction; Iterative algorithms; Postal services; Prediction algorithms; Reactive power; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757380

Filename

757380