Title :
Novel design for testability of a mixed-signal VLSIC
Author :
McShane, E. ; Shenai, K. ; Alkalai, L. ; Kolawa, E. ; Boyadzhyan, V. ; Blaes, B. ; Fang, W.C.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA
Abstract :
A novel testability architecture has been developed for a mixed-signal VLSIC which has a functional architecture consisting of a microprocessor core, RF transceiver, and two voltage regulators. It permits a decoupling of analog/RF, digital, and power systems for individual stimulation and analysis. Testing may be performed at the subsystem or block level, and traditional scan techniques are augmented to allow mixed static and dynamic test. This approach aids in identifying any detrimental interaction between individual subsystems by providing isolation between the circuit-under-test and idle circuits
Keywords :
CMOS integrated circuits; VLSI; design for testability; integrated circuit design; integrated circuit testing; mixed analogue-digital integrated circuits; DFT; RF transceiver; block level testing; design for testability; isolation; microprocessor core; mixed static/dynamic testing; mixed-signal VLSI chips; scan techniques; subsystem level testing; testability architecture; voltage regulators; Circuit testing; Design for testability; Microprocessors; Performance evaluation; Power system analysis computing; Power system dynamics; Radio frequency; Regulators; Transceivers; Voltage;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757385
