Title :
Power and thermal constrained test scheduling
Author :
YAo, Chunhua ; Saluja, Kewal K. ; Ramanathan, Parameswaran
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA
Abstract :
We propose a test scheduling algorithm that ensures the resource compatibility and satisfies both power and thermal constraints. The proposed algorithm can start a test at an arbitrary time and it has the capability of delaying a test to let a core cool down to find a valid schedule even when traditional scheduling schemes cannot find a solution. To reduce the execution time of thermal simulation, we exploit superposition principle to compute the thermal profile rapidly and accurately. We apply our scheduling algorithm to ITC´02 SoC benchmarks and the results show a remarkable improvement in the total test length over other methods, while meeting the thermal and power constraints.
Keywords :
benchmark testing; integrated circuit testing; scheduling; system-on-chip; ITC´02 SoC benchmarks; power constraint; resource compatibility; superposition principle; test scheduling algorithm; thermal constraint; thermal profile; Benchmark testing; Computational modeling; Cooling; Design engineering; Energy consumption; Processor scheduling; Quantum computing; Scheduling algorithm; Temperature; Thermal engineering;
Conference_Titel :
Test Conference, 2009. ITC 2009. International
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4868-5
Electronic_ISBN :
978-1-4244-4867-8
DOI :
10.1109/TEST.2009.5355630