Design issues in synthesis of reusable cores

While core-based design is itself a challenging task, it is equally challenging for a core vendor to provide information about a core without compromising on the protection of intellectual property. A number of issues are to be taken into consideration when designing a core. While conventional goals such as minimal area and maximal performance continue to hold, additional constraints such as core testability and power dissipation will have to be considered. Since the vendor of a core does not reveal details about the internals of the core, it is often the responsibility of the vendor to provide the test plan for the core. In this paper, we present our experiences in designing a testable CORDIC core