Effective self-test routine for on-line testing of processors implemented in harsh environments

Today, it is a common practice to test commercial off-the-shelf (COTS) processors with self-test routines. Faults in processors may cause failure in self-test routine execution, which is one of the essential disadvantages of these routines. In this paper, we present an effective register transfer level (RTL) method to develop on-line self-test routines. Our proposed method prioritizes components and instructions of processor to select instructions, and applies spectral RTL test pattern generation (TPG) strategy to select test patterns. This method analyzes the spectrum and the noise level with Walsh functions. Also, we use a few extra instructions for the purpose of the signature monitoring to detect control flow errors. We demonstrate that the combination of these three strategies is effective for developing small test programs with high fault coverage in a small test development time. This approach requires only instruction set architecture (ISA) and RTL information of the processors. Since proposed method is based on RTL test generation, it has the advantages of lower memory and test generation time complexities. We develop a self-test routine using our proposed method for Parwan processor and demonstrate the effectiveness of our proposed methodology for on-line testing by presenting experimental results for Parwan processor.