Title :
Parallel saturating fractional arithmetic units
Author :
Yadav, Navindra ; Schulte, Michael ; Glossner, John
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Lehigh Univ., Bethlehem, PA, USA
Abstract :
This paper describes the designs of a saturating adder multiplier single MAC unit, and dual MAC unit with single cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output of the dual MAC unit is identical to the result of the operations performed serially with saturation after each multiplication and each addition
Keywords :
adders; digital arithmetic; digital signal processing chips; multiplying circuits; parallel processing; dual MAC unit; fractional arithmetic units; parallel operations; saturating adder multiplier; saturation logic; single MAC unit; single cycle latencies; Adders; Arithmetic; Circuits; Decoding; Delay estimation; Digital signal processing; GSM; Logic; Mobile communication; Speech;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757413
