A 295 MHz CMOS 1 M (/spl times/256) embedded SRAM using bi-directional read/write shared sense amps and self-timed pulsed word-line drivers

Author

Kushiyama, N. ; Tan, C. ; Clark, R. ; Lin, J. ; Pemer, F. ; Martin, L. ; Leonard, M. ; Coussens, G. ; Cham, K. ; Chiu, K.

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kanagawa, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

304

Lastpage

305

Abstract

This SRAM explores the feasibility of the mid-capacity, wideword, very high-speed embedded memories for the over-200 MHz generation of MPUs. The SRAM is fabricated in a 0.35 /spl mu/m CMOS quadruple-metal process. It has 1 Mb capacity and 256 b of full-differential 0.3 V-swing I/O. A bidirectional read/write shared sense amp (BSA) and self-timed pulsed word-line (SPW) are used to reduce power consumption, save chip area, and improve performance.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit design; integrated circuit technology; very high speed integrated circuits; 0.35 micron; 1 Mbit; 295 MHz; CMOS; bi-directional read/write shared sense amps; chip area; embedded SRAM; full-differential I/O; power consumption; quadruple-metal process; self-timed pulsed word-line drivers; very high-speed embedded memories; Bandwidth; Bidirectional control; CMOS technology; Circuits; Clocks; Energy consumption; Latches; Process design; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535566

Filename

535566