• DocumentCode
    2704089
  • Title

    An incremental floorplanner

  • Author

    Crenshaw, Jim ; Sarrafzadeh, Majid ; Banerjee, Prithviraj ; Prabhakaran, Pradeep

  • Author_Institution
    Corp. Res. Labs., Motorola Inc., USA
  • fYear
    1999
  • fDate
    4-6 Mar 1999
  • Firstpage
    248
  • Lastpage
    251
  • Abstract
    One of the foremost problems in physical design for deep-submicron circuits is the need for estimates that depend on future decisions. Estimation of area, timing, and coupling are required. We propose a novel floorplanner, with a new wiring metric, which can be updated quickly in small increments. This provides tools with a way to influence the floorplan as they make changes without large running time penalty. We provide experimental results that show the incremental approach to be generally 5 times faster than full floorplanning while maintaining good estimates
  • Keywords
    computational complexity; high level synthesis; integrated circuit layout; logic partitioning; minimisation; area; coupling; deep-submicron circuits; timing; wiring metric; Birth disorders; Capacitance; Clocks; Contracts; Coupling circuits; Delay; Design automation; High level synthesis; Process design; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
  • Conference_Location
    Ypsilanti, MI
  • ISSN
    1066-1395
  • Print_ISBN
    0-7695-0104-4
  • Type

    conf

  • DOI
    10.1109/GLSV.1999.757426
  • Filename
    757426