Title :
A greedy router with technology targetable output
Author :
Balakrishnan, R. ; Hobson, R.F.
Author_Institution :
Sch. of Comput. & Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
Abstract :
Our objective was to integrate an effective channel routing algorithm with the Chip Design Language (CDL) algorithmic layout tool. CDL uses technology targetable layout techniques, so that the output of the routing algorithm can easily be ported to different technologies. We introduce the technology independent features of CDL and describe how a greedy router can be interfaced to it. Specific features of interest include mapping from the grid based router to the gridless CDL environment, and the automatic insertion of CDL feed-through cells in multi-channel applications
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; network routing; CDL feed-through cells; Chip Design Language; algorithmic layout tool; automatic insertion; effective channel routing; greedy router; grid based router; mapping; multi-channel applications; routing algorithm; technology targetable layout; technology targetable output; Chip scale packaging; Circuit simulation; Computer languages; Data structures; Heuristic algorithms; Identity-based encryption; Libraries; Microwave integrated circuits; Read only memory; Routing;
Conference_Titel :
VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on
Conference_Location :
Ypsilanti, MI
Print_ISBN :
0-7695-0104-4
DOI :
10.1109/GLSV.1999.757427
