Memory unit design for real time DSP applications

Today, the design complexity for new applications (such as telecommunication, multi media, internet), requires new high level tools which enable us to translate the behavioral description into hardware. All of the recent High Level Synthesis tools are able to transform high level specifications in an ASIC based on processing and control units. In general, these tools do not handle a real optimization of the memory unit. However, in many applications, the hardware solution may be challenged by the number and the complexity of memory units. This paper proposes to complete the synthesis design flow by including the memory unit synthesis. Our methodology is integrated in the BSS (Breizh Synthesis System http://www.enssat.fr/bss) project which is a framework for the design of real-time constraint applications